The present invention relates to a semiconductor integrated circuit device including a plurality of microprocessors and, more particularly, to a technique for facilitating debugging in the semiconductor integrated circuit device.
A semiconductor integrated circuit device in which a plurality of microprocessors are formed on a single semiconductor substrate is a technique attracting attention in recent years.
As a method of debugging a semiconductor integrated circuit device including a plurality of microprocessors, a first technique is known in which a group of debug terminals of the same number as that of mounted processors is provide for a semiconductor integrated circuit device, and debugging devices are connected to the terminals, thereby individually debugging any of the processors by using the corresponding debugging device. A second technique is also known in which a debug terminal group is provided for a semiconductor integrated circuit device, and TAP controllers connected to processors are connected in series, thereby debugging all of the processors by using one debugging device (refer to, for example, the second and third paragraphs in Japanese Unexamined Patent Publication No. 2004-164367).
Further, a third technique is also known which provides: a plurality of processors; a debug executing unit for executing debugging of the plurality of processors; a TAP (Test Access Port) for controlling the debug executing unit; a terminal group connected to an external debugging apparatus; and a selector for selecting at least one or all of processors to be subjected to the debugging. With the configuration, a processor to be debugged can be selected (refer to, for example, the nine and subsequent paragraphs in Japanese Unexamined Patent Publication No. 2004-164367).